Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.

ARM EN0-001 Question Answer

LDR r0, [r1]

STR r0, [r2]

STR r3, [r3]

R1 points to a location in normal memory. R2 and R3 point to device memory.

Which of the following statements best describes the ordering rules which apply to this sequence?

The two writes to device memory will happen in program order, but the read can be performed out of order

The memory accesses can happen in any order

The memory accesses will happen in program order

The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order

EN0-001 PDF/Engine

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